The present invention generally relates to integrated circuits, and more particularly, to a design for an access cell and a method for enabling automatic insertion of access cells into an integrated circuit design.
The process of designing an integrated circuit may involve inserting a set of access cells into the integrated circuit design to enable reconfiguration of the integrated circuit in the event that post fabrication testing reveals a design flaw in the circuit. More particularly, the design process results in a layout that represents the physical structure of the integrated circuit and that layout is used to fabricate a limited number of the integrated circuit for testing purposes. The test circuits are typically subjected to a battery of tests related to both the functionality of the circuit and the physical characteristics of the circuit. If, during testing, the circuit does not operate as desired, then a logic circuit associated with the integrated circuit is examined to identify one or more cells responsible for the undesired operation.
As will be understood by one having ordinary skill in the art, integrated circuits are designed to perform a set of functions that are implemented using a variety of structures referred to as cells. Included among these cells are logic cells that are designed to perform any of a set of logical operations such as AND, OR, NOR, etc., and the cells are coupled together to form the logic circuit which causes the integrated circuit to perform the desired set of functions. In many instances, undesired operation detected during testing may be corrected by using access cells to reconfigure the logic circuit and remove the logic cell(s) responsible for the undesired operation and/or to add one or more spare logic cells to the logic circuit. Thus, in addition to logic cells, the integrated circuit also includes a set of access cells that facilitate the removal of one or more logic cells from the logic circuit and/or the addition of one or more spare logic cells to the logic circuit. The spare logic cells, which are disposed at various locations throughout the integrated circuit, are referred to as xe2x80x9csparexe2x80x9d cells because, although each is capable of performing a desired logical operation, these spare logic cells are not coupled to the logic circuit and, as a result, do not affect circuit operation.
To facilitate reconfiguration of the logic circuit, each access cell provides a path through which current may be routed from a first logic cell to a second logic cell. The configuration of the current path may be physically altered to cause the current flowing through the path to be rerouted so that instead of flowing from the first logic cell to the second logic cell, the current flows from the first logic cell to a spare logic cell. In this manner, the access cell may be used to insert the spare logic cell into the logic circuit and remove, for example, the second logic cell from the logic circuit. Alternatively, the current may be redirected to flow from the spare logic to the second logic cell thereby removing the first logic cell from the circuit.
Unfortunately, the methods that are currently available for inserting access cells into an integrated circuit design are costly, time consuming, and/or unreliable. In particular, a first method for access cell insertion is performed manually. Using this method, after the layout of the integrated circuit has been created, the locations at which the access cells will be inserted into the design are determined manually by a design engineer. The design engineer uses the layout to identify desired positions at which the access cells may be inserted in the integrated circuit design. Often parts of the layout will have to be spread out in order to create a hole large enough for the access cell. All of the positions that are deemed suitable are then incorporated manually into the layout design. Although this manual insertion method is effective, it is time consuming, tedious and costly in terms of engineering hours. In addition, the design process is iterative so that a layout may be revised many times, each time resulting in a differently configured layout, thereby requiring that the locations at which the access cells be inserted be determined over again. Moreover, as with most industries, integrated circuit design processes are becoming increasingly more automated. As a result, manual design processes are generally less favored.
A second method of access cell insertion is performed using a xe2x80x9cplace and routexe2x80x9d tool. As will be understood by one having ordinary skill in the art, a place and route tool is a software tool used to create a layout for an integrated circuit design. Before the place and route tool is used, a set of access cells are added to a netlist. As will be understood by one having ordinary skill in the art, the netlist is a listing of the logic cells required to implement the functionality of the integrated circuit and the netlist also provides the connectivity between the listed cells. The access cells added to the netlist are each described in the netlist as being single terminal cells. As will be understood by one having ordinary skill in the art, a single terminal cell is connected to a single net, or wire. However, place and route tools often cause single terminal cells to be inserted in a manner such that the access cell is coupled to only a single logic cell. As a result, current does not completely route through the access cell, i.e., into and out of the access cell, but is instead only routed into the access cell. Thus, the designer cannot use the access cell to reconfigure the circuit in the manner described above, e.g., from a first cell to a spare cell instead of from a first cell to a second cell, thereby defeating the purpose of inserting the access cell into the circuit. Methods have been used to increase the likelihood that complete route through is achieved by using statistics to identify locations in the circuit at which access cell placement is more likely to result in complete route through. However, these statistical methods do not guarantee complete route through and often result in suboptimal placement of access cells in the layout.
Alternatively, the access cells have been described in the netlist as two terminal cells. Describing the access cells as two terminal cells in the netlist ensures that the place and route tool inserts the access cell in a manner that guarantees complete route through. Thus, the access cell is shown as being connected to a first net at a first terminal and a second net at a second terminal in the resulting layout. However, because the access cell does not perform any logical operation on the current routed therethrough, the access cell is not actually connected to two different nets but will instead actually be connected to a single net that has been severed in half. Specifically, the access cell is actually connected at the first terminal to a first half of the net and at the second terminal to the second half of the net. Thus, a single net is represented in the resulting layout as two different nets, but is still represented in the netlist as a single net. However, in order to effectively test and debug the design of the integrated circuit, the resulting layout and the netlist must coincide or else errors are generated thereby hindering the testing and debugging process.
Moreover, access cells present challenges to integrated circuit designers beyond those associated with inserting the cells. Specifically, there is an on-going effort to further miniaturize integrated circuits. As a result, space on an integrated circuit must be optimized thereby causing designers, where possible, to use cells having the smallest permissible dimensions. For example, the smallest permissible dimensions of an access cell are dictated, at least in part, by the precision of a focused ion beam used to sever the pathway routed through the access cell. More particularly, the access cell must be at least a minimum size to ensure that there is sufficient room between the access cell and neighboring cells so that the neighboring cells are not inadvertently damaged or destroyed when the FIB is used to sever the pathway to enable current reconfiguration. Thus, ideally, access cells having the minimum permissible size are selected for insertion into the integrated circuit. However, access cells must also comply with a set of spacing requirements that specify minimum distances between various features of the access cell. Unfortunately, access cells having typical pathway configurations must often be larger than the minimum permissible size so that these spacing requirements are met. Further, in order to provide a space large enough to fit the access cell, the overall size of the integrated circuit must often be increased.
Thus, there is a need in the art for a method for enabling automatic insertion of access cells into an integrated circuit design that ensures that the access cells are 1) inserted in a manner such that they are usable for their intended purpose, i.e., so that complete route through is achieved, and 2) inserted in a manner that does not adversely affect testing of the integrated circuit. In addition, there is a further need in the art for an access cell having a pathway configuration that satisfies the minimum spacing requirements associated with the access cell without adversely impacting the overall dimensions of the access cell.